Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/DV-CPU-RV@2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf dv-cpu-rv
[Pipeline] sh
+ git clone --recursive https://github.com/devindang/dv-cpu-rv dv-cpu-rv
Cloning into 'dv-cpu-rv'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV@2/dv-cpu-rv
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_div.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v
core/rtl/rv_core.v:320: error: Unknown module type: rv_instr_mem
core/rtl/rv_core.v:366: error: Unknown module type: rv_branch_test
core/rtl/rv_core.v:379: error: Unknown module type: rv_data_mem
4 error(s) during elaboration.
*** These modules were missing:
        rv_branch_test referenced 1 times.
        rv_data_mem referenced 1 times.
        rv_instr_mem referenced 1 times.
***
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV@2/dv-cpu-rv
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE README.md README_zh_CN.md clean.pl core docs refs src
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 4
Finished: FAILURE