Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/DV-CPU-RV
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf AUK-V-Aethia
[Pipeline] sh
+ git clone --recursive https://github.com/veeYceeY/AUK-V-Aethia AUK-V-Aethia
Cloning into 'AUK-V-Aethia'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s aukv rtl/core/aukv.v rtl/core/aukv_alu.v rtl/core/aukv_csr_regfile.v rtl/core/aukv_decode.v rtl/core/aukv_execute.v rtl/core/aukv_fetch.v rtl/core/aukv_gpr_regfilie.v rtl/core/aukv_mem.v
+ vvp simulation.out
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia
[Pipeline] {
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b colorlight_i9
[Pipeline] sh
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia/build_colorlight_i9.tcl
Erro ao executar o Makefile.
ERROR: Output port top.Controller.core_read_data_memory ($paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller) is connected to constants: { $auto$hierarchy.cc:1460:execute$1428 1'1 }
make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:13: colorlight_i9.json] Error 1

+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr
Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
Stage "Teste colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Aborted by Julio Nunes Avelar
Sending interrupt signal to process
Sending interrupt signal to process
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
Terminated
Terminated
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 143

Terminated
script returned exit code 143
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Click here to forcibly terminate running steps
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/DV-CPU-RV/AUK-V-Aethia
[Pipeline] {
[Pipeline] sh
+ rm -rf LICENSE README.md build_colorlight_i9.tcl build_digilent_nexys4_ddr.tcl doc rtl simulation.out sw tb
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: ABORTED