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Start of Pipeline - (24 sec in block)
node - (23 sec in block)
node block - (22 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (3 sec in block)
sh - (0.51 sec in self)rm -rf dv-cpu-rv
sh - (2.2 sec in self)git clone --recursive https://github.com/devindang/dv-cpu-rv dv-cpu-rv
stage - (2.2 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)dv-cpu-rv
dir block - (0.72 sec in block)
sh - (0.48 sec in self)iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_div.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v && vvp simulation.out
stage - (13 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (12 sec in block)
getContext - (0.3 sec in self)
parallel - (11 sec in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (8.8 sec in block)colorlight_i9
stage block (colorlight_i9) - (7.9 sec in block)
getContext - (0.7 sec in self)
stage - (2 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.72 sec in block)
getContext - (0.2 sec in self)
stage - (2.2 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.81 sec in block)
getContext - (0.31 sec in self)
stage - (1.7 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.6 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (10 sec in block)
stage - (8.9 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (7.9 sec in block)
getContext - (0.67 sec in self)
stage - (2 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (0.8 sec in block)
getContext - (0.16 sec in self)
stage - (2.1 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.88 sec in block)
getContext - (0.17 sec in self)
stage - (1.9 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.95 sec in block)
getContext - (0.38 sec in self)
stage - (3.2 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.5 sec in block)
dir - (1.4 sec in block)dv-cpu-rv
dir block - (1 sec in block)
sh - (0.57 sec in self)rm -rf *