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Start of Pipeline - (7 min 14 sec in block)
node - (7 min 13 sec in block)
node block - (6 min 5 sec in block)
stage - (3.7 sec in block)Git Clone
stage block (Git Clone) - (3.1 sec in block)
sh - (1.1 sec in self)rm -rf pulpino
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/pulp-platform/pulpino pulpino
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.96 sec in block)
dir - (0.6 sec in block)pulpino
dir block - (0.33 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)pulpino
dir block - (0.61 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (5 min 57 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 56 sec in block)
parallel - (5 min 56 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (12 sec in block)colorlight_i9
stage block (colorlight_i9) - (12 sec in block)
lock - (11 sec in block)colorlight_i9
lock block - (11 sec in block)
stage - (8.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (8.1 sec in block)
dir - (7.6 sec in block)pulpino
dir block - (7.3 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (6.9 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p pulpino -b colorlight_i9
stage - (0.98 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.37 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (5 min 55 sec in block)
stage - (5 min 54 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 54 sec in block)
lock - (5 min 52 sec in block)digilent_arty_a7_100t
lock block - (1 min 12 sec in block)
stage - (1 min 10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 9 sec in block)
dir - (1 min 9 sec in block)pulpino
dir block - (1 min 8 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p pulpino -b digilent_arty_a7_100t
stage - (0.93 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.66 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.24 sec in self)**/test-reports/*.xml