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Start of Pipeline - (9 min 46 sec in block)
node - (9 min 45 sec in block)
node block - (9 min 44 sec in block)
stage - (7.7 sec in block)Git Clone
stage block (Git Clone) - (6.7 sec in block)
sh - (0.67 sec in self)rm -rf VexRiscv
sh - (5.6 sec in self)git clone --recursive https://github.com/SpinalHDL/VexRiscv VexRiscv
stage - (2 min 30 sec in block)Verilog Convert
stage block (Verilog Convert) - (2 min 30 sec in block)
dir - (2 min 29 sec in block)VexRiscv
dir block - (2 min 29 sec in block)
sh - (2 min 29 sec in self)sbt "runMain vexriscv.demo.GenFull"
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.1 sec in block)
dir - (0.81 sec in block)VexRiscv
dir block - (0.58 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s VexRiscv VexRiscv.v
stage - (7 min 2 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (7 min 2 sec in block)
parallel - (7 min 1 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (3 min 30 sec in block)colorlight_i9
stage block (colorlight_i9) - (3 min 30 sec in block)
lock - (3 min 29 sec in block)colorlight_i9
lock block - (3 min 29 sec in block)
stage - (3 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3 min 7 sec in block)
dir - (3 min 7 sec in block)VexRiscv
dir block - (3 min 7 sec in block)
echo - (0.15 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (3 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9
stage - (14 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (13 sec in block)
dir - (13 sec in block)VexRiscv
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9 -l
stage - (6.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.5 sec in block)VexRiscv
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (7 min 1 sec in block)
stage - (7 min 0 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (7 min 0 sec in block)
lock - (6 min 59 sec in block)digilent_nexys4_ddr
lock block - (4 min 54 sec in block)
stage - (4 min 38 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 38 sec in block)
dir - (4 min 37 sec in block)VexRiscv
dir block - (4 min 37 sec in block)
echo - (0.4 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr
stage - (13 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)VexRiscv
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr -l
stage - (1.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.96 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.41 sec in block)VexRiscv
dir block - (0.15 sec in block)
stage - (1.1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.88 sec in block)
junit - (0.63 sec in self)**/test-reports/*.xml