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Build #40

Console
Pipeline
Git Clone
Verilog Convert
Simulation
Síntese e PnR
Flash colorlight_i9
Teste colorlight_i9
Síntese e PnR
Flash digilent_nexys4_ddr
Teste digilent_nexys4_ddr
Post Actions
Start
Git Clone
Verilog Co…
Simulation
FPGA Build P…
Post Actions
End
Síntese e PnR
Flash colorlight_i9
Teste colorlight_i9
Síntese e PnR
Flash digilent_…
Teste digilent_…
colorlight_i9
digilent_nexys4_ddr
Details

Started 5 mo 18 days ago

Queued 78 ms

Took 9 min 47 sec