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Start of Pipeline - (3 min 20 sec in block)
node - (3 min 20 sec in block)
node block - (3 min 19 sec in block)
stage - (4.8 sec in block)Git Clone
stage block (Git Clone) - (4.2 sec in block)
sh - (0.46 sec in self)rm -rf VexRiscv
sh - (3.6 sec in self)git clone --recursive https://github.com/SpinalHDL/VexRiscv VexRiscv
stage - (2 min 56 sec in block)Verilog Convert
stage block (Verilog Convert) - (2 min 56 sec in block)
dir - (2 min 55 sec in block)VexRiscv
dir block - (2 min 55 sec in block)
sh - (2 min 55 sec in self)sbt "runMain vexriscv.demo.GenFull"
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)VexRiscv
dir block - (0.62 sec in block)
sh - (0.41 sec in self)iverilog -o simulation.out -g2005 -s VexRiscv VexRiscv.v
stage - (13 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (13 sec in block)
parallel - (12 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (11 sec in block)colorlight_i9
stage block (colorlight_i9) - (10 sec in block)
lock - (9.5 sec in block)colorlight_i9
lock block - (8.6 sec in block)
stage - (4.1 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3 sec in block)
dir - (2 sec in block)VexRiscv
dir block - (1.6 sec in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (0.99 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9
stage - (1.9 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.64 sec in block)
getContext - (0.16 sec in self)
stage - (1.3 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.67 sec in block)
getContext - (0.2 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (12 sec in block)
stage - (11 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (10 sec in block)
lock - (9.3 sec in block)digilent_nexys4_ddr
lock block - (8.4 sec in block)
stage - (4.1 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (2.9 sec in block)
dir - (1.9 sec in block)VexRiscv
dir block - (1.4 sec in block)
echo - (0.23 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (0.68 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr
stage - (1.9 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.82 sec in block)
getContext - (0.2 sec in self)
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.78 sec in block)
getContext - (0.16 sec in self)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.3 sec in block)
dir - (0.87 sec in block)VexRiscv
dir block - (0.61 sec in block)
sh - (0.41 sec in self)rm -rf *