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Started by user Julio Nunes Avelar [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/VexRiscv [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf VexRiscv [Pipeline] sh + git clone --recursive https://github.com/SpinalHDL/VexRiscv VexRiscv Cloning into 'VexRiscv'... Submodule 'src/test/resources/VexRiscvRegressionData' (https://github.com/SpinalHDL/VexRiscvRegressionData.git) registered for path 'src/test/resources/VexRiscvRegressionData' Cloning into '/var/lib/jenkins/workspace/VexRiscv/VexRiscv/src/test/resources/VexRiscvRegressionData'... Submodule path 'src/test/resources/VexRiscvRegressionData': checked out '539398c1481203a51115b5f1228ea961f0ac9bd3' [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Verilog Convert) [Pipeline] dir Running in /var/lib/jenkins/workspace/VexRiscv/VexRiscv [Pipeline] { [Pipeline] sh + sbt runMain vexriscv.demo.GenFull downloading sbt launcher 1.9.7 perl: warning: Setting locale failed. perl: warning: Please check that your locale settings: LANGUAGE = (unset), LC_ALL = (unset), LANG = "pt_PT.UTF-8" are supported and installed on your system. perl: warning: Falling back to the standard locale ("C"). copying runtime jar... [info] [launcher] getting org.scala-sbt sbt 1.6.0 (this may take some time)... [info] [launcher] getting Scala 2.12.15 (for sbt)... [0m[[0m[0minfo[0m] [0m[0mwelcome to sbt 1.6.0 (Ubuntu Java 17.0.12)[0m [0m[[0m[0minfo[0m] [0m[0mloading settings for project vexriscv-build from plugins.sbt ...[0m [0m[[0m[0minfo[0m] [0m[0mloading project definition from /var/lib/jenkins/workspace/VexRiscv/VexRiscv/project[0m [0m[[0m[0minfo[0m] [0m[0mloading settings for project root from build.sbt ...[0m [0m[[0m[0minfo[0m] [0m[0mset current project to VexRiscv (in build file:/var/lib/jenkins/workspace/VexRiscv/VexRiscv/)[0m [0m[[0m[0minfo[0m] [0m[0mcompiling 97 Scala sources to /var/lib/jenkins/workspace/VexRiscv/VexRiscv/target/scala-2.12/classes ...[0m [0m[[0m[0minfo[0m] [0m[0mNon-compiled module 'compiler-bridge_2.12' for Scala 2.12.18. Compiling...[0m [0m[[0m[0minfo[0m] [0m[0m Compilation completed in 21.074s.[0m [0m[[0m[33mwarn[0m] [0m[0m/var/lib/jenkins/workspace/VexRiscv/VexRiscv/src/main/scala/vexriscv/VexRiscv.scala:36:17: match may not be exhaustive.[0m [0m[[0m[33mwarn[0m] [0m[0mIt would fail on the following input: None[0m [0m[[0m[33mwarn[0m] [0m[0m plugins.find(_.getClass == clazz) match {[0m [0m[[0m[33mwarn[0m] [0m[0m ^[0m [0m[[0m[33mwarn[0m] [0m[0m/var/lib/jenkins/workspace/VexRiscv/VexRiscv/src/main/scala/vexriscv/plugin/BranchPlugin.scala:159:5: match may not be exhaustive.[0m [0m[[0m[33mwarn[0m] [0m[0mIt would fail on the following input: (FetchPredictionBus(_), DecodePredictionBus(_))[0m [0m[[0m[33mwarn[0m] [0m[0m (fetchPrediction,decodePrediction) match {[0m [0m[[0m[33mwarn[0m] [0m[0m ^[0m [0m[[0m[0minfo[0m] [0m[0m/var/lib/jenkins/workspace/VexRiscv/VexRiscv/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala:1:1: [0m [0m[[0m[0minfo[0m] [0m[0mFound names but no class, trait or object is defined in the compilation unit.[0m [0m[[0m[0minfo[0m] [0m[0mThe incremental compiler cannot record the dependency information in such case.[0m [0m[[0m[0minfo[0m] [0m[0mSome errors like unused import referring to a non-existent class might not be reported.[0m [0m[[0m[0minfo[0m] [0m[0m [0m [0m[[0m[0minfo[0m] [0m[0mpackage vexriscv.demo.smp[0m [0m[[0m[0minfo[0m] [0m[0m^[0m [0m[[0m[0minfo[0m] [0m[0m/var/lib/jenkins/workspace/VexRiscv/VexRiscv/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala:1:1: [0m [0m[[0m[0minfo[0m] [0m[0mFound top level imports but no class, trait or object is defined in the compilation unit.[0m [0m[[0m[0minfo[0m] [0m[0mThe incremental compiler cannot record the dependency information in such case.[0m [0m[[0m[0minfo[0m] [0m[0mSome errors like unused import referring to a non-existent class might not be reported.[0m [0m[[0m[0minfo[0m] [0m[0m [0m [0m[[0m[0minfo[0m] [0m[0mpackage vexriscv.demo.smp[0m [0m[[0m[0minfo[0m] [0m[0m^[0m [0m[[0m[33mwarn[0m] [0m[0m157 deprecations[0m [0m[[0m[33mwarn[0m] [0m[0m17 deprecations (since 1.3.0)[0m [0m[[0m[33mwarn[0m] [0m[0mone deprecation (since ???)[0m [0m[[0m[33mwarn[0m] [0m[0m20 deprecations (since SpinalHDL 1.3.1)[0m [0m[[0m[33mwarn[0m] [0m[0m195 deprecations in total; re-run with -deprecation for details[0m [0m[[0m[33mwarn[0m] [0m[0mtwo feature warnings; re-run with -feature for details[0m [0m[[0m[33mwarn[0m] [0m[0m8 warnings found[0m [0m[[0m[0minfo[0m] [0m[0mdone compiling[0m [0m[[0m[0minfo[0m] [0m[0mrunning (fork) vexriscv.demo.GenFull [0m [0m[[0m[0minfo[0m] [0m[0m[Runtime] SpinalHDL v1.10.2a git head : a348a60b7e8b6a455c72e1536ec3d74a2ea16935[0m [0m[[0m[0minfo[0m] [0m[0m[Runtime] JVM max memory : 3990.0MiB[0m [0m[[0m[0minfo[0m] [0m[0m[Runtime] Current date : 2024.10.07 23:42:47[0m [0m[[0m[0minfo[0m] [0m[0m[Progress] at 0.000 : Elaborate components[0m [0m[[0m[0minfo[0m] [0m[0m[Warning] This VexRiscv configuration is set without software ebreak instruction support. Some software may rely on it (ex: Rust). (This isn't related to JTAG ebreak)[0m [0m[[0m[0minfo[0m] [0m[0m[Progress] at 3.063 : Checks and transforms[0m [0m[[0m[0minfo[0m] [0m[0m[Progress] at 4.257 : Generate Verilog to .[0m [0m[[0m[0minfo[0m] [0m[0m[Warning] 219 signals were pruned. You can call printPruned on the backend report to get more informations.[0m [0m[[0m[0minfo[0m] [0m[0m[Done] at 4.979[0m [0m[[0m[32msuccess[0m] [0m[0mTotal time: 136 s (02:16), completed Oct 7, 2024, 11:42:52 PM[0m [0J [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/lib/jenkins/workspace/VexRiscv/VexRiscv [Pipeline] { [Pipeline] sh + iverilog -o simulation.out -g2005 -s VexRiscv VexRiscv.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] Resource [digilent_nexys4_ddr] did not exist. Created. Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] { [Pipeline] stage [Pipeline] { (Síntese e PnR) [Pipeline] stage [Pipeline] { (Síntese e PnR) [Pipeline] dir Running in /var/lib/jenkins/workspace/VexRiscv/VexRiscv [Pipeline] { [Pipeline] dir Running in /var/lib/jenkins/workspace/VexRiscv/VexRiscv [Pipeline] { [Pipeline] echo Iniciando síntese para FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Iniciando síntese para FPGA digilent_nexys4_ddr. + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b colorlight_i9 [Pipeline] sh Traceback (most recent call last): File "/eda/processor-ci/main.py", line 79, in <module> main( File "/eda/processor-ci/main.py", line 17, in main processor_data = get_processor_data(config, processor_name) File "/eda/processor-ci/core/config.py", line 46, in get_processor_data raise ValueError( ValueError: Processador 'VexRiscv' n��o encontrado na configura����o. + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p VexRiscv -b digilent_nexys4_ddr Traceback (most recent call last): File "/eda/processor-ci/main.py", line 79, in <module> main( File "/eda/processor-ci/main.py", line 17, in main processor_data = get_processor_data(config, processor_name) File "/eda/processor-ci/core/config.py", line 46, in get_processor_data raise ValueError( ValueError: Processador 'VexRiscv' n��o encontrado na configura����o. [Pipeline] } [Pipeline] } [Pipeline] // dir [Pipeline] // dir [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] stage [Pipeline] { (Teste colorlight_i9) [Pipeline] stage [Pipeline] { (Teste digilent_nexys4_ddr) Stage "Teste colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 [Pipeline] } Failed in branch digilent_nexys4_ddr [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] dir Running in /var/lib/jenkins/workspace/VexRiscv/VexRiscv [Pipeline] { [Pipeline] sh + rm -rf LICENSE README.md VexRiscv.v assets build.sbt build.sc cpu0.yaml doc project scripts simulation.out src target tools.sh [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE