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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/T03x [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf T03x [Pipeline] sh + git clone --recursive --depth=1 https://github.com/klessydra/T03x T03x Cloning into 'T03x'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/T03x/T03x [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-t0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/PKG_RiscV_Klessydra.vhd klessydra-t0-3th/RTL-CSR_Unit.vhd klessydra-t0-3th/RTL-Debug_Unit.vhd klessydra-t0-3th/RTL-Processing_Pipeline.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd klessydra-t0-3th/STR-Klessydra_top.vhd klessydra-t0-3th/RTL-Program_Counter_unit.vhd:79:12:warning: declaration of "MTVEC" hides port "MTVEC" [-Whide] signal MTVEC : in std_logic_vector(31 downto 0); ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:80:12:warning: declaration of "instr_gnt_i" hides port "instr_gnt_i" [-Whide] signal instr_gnt_i, taken_branch : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:80:25:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide] signal instr_gnt_i, taken_branch : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:81:12:warning: declaration of "wfi_condition_pending" hides signal "wfi_condition_pending" [-Whide] signal wfi_condition_pending : inout std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:82:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide] signal set_wfi_condition : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:83:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide] signal taken_branch_pending : inout std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:84:12:warning: declaration of "irq_pending" hides port "irq_pending" [-Whide] signal irq_pending : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:85:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide] signal set_except_condition : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:86:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide] signal set_mret_condition : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:87:12:warning: declaration of "pc" hides signal "pc" [-Whide] signal pc : inout std_logic_vector(31 downto 0); ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:88:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide] signal taken_branch_pc_lat : in std_logic_vector(31 downto 0); ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:89:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide] signal incremented_pc : in std_logic_vector(31 downto 0); ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:90:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide] signal boot_pc : in std_logic_vector(31 downto 0); ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:91:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide] signal pc_update_enable : in std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:92:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide] signal served_except_condition : out std_logic; ^ klessydra-t0-3th/RTL-Program_Counter_unit.vhd:93:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide] signal served_mret_condition : out std_logic) is ^ [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/T03x/T03x [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/T03x/T03x -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels WARNING: No LICENSE files found. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build Cores-SweRV #181 #181 since Apr 7, 2025, 2:17 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 0 [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/T03x/T03x [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p T03x -b colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/T03x/T03x/build_colorlight_i9.tcl Error executing Makefile. ERROR: TCL interpreter returned an error: Yosys command produced an error make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/T03x/T03x [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p T03x -b digilent_arty_a7_100t Final configuration file generated at /var/jenkins_home/workspace/T03x/T03x/build_digilent_arty_a7_100t.tcl Error executing Makefile. ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/modules/uart.v' does not exist make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 68dde6a6-b553-4b30-84a1-682d2a0b5e07 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE