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Started by user Julio Nunes Avelar [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/Cores-SweRV [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf *.xml [Pipeline] sh + rm -rf Cores-SweRV [Pipeline] sh + git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV Cores-SweRV Cloning into 'Cores-SweRV'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Verilog Convert) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV [Pipeline] { [Pipeline] sh + pwd + RV_ROOT=/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV configs/veer.config -set=fpga_optimize=1 -target=default -set=btb_size=128 veer: Set(s) requested : fpga_optimize=1 btb_size=128 veer: Overriding btb_size value 32 with 128 VeeR configuration for target=default veer: external_mem_hole = default disabled veer: iccm_region = 0xe veer: iccm_offset = 0xe000000 veer: iccm_num_banks = 8 veer: iccm_size = 512 veer: ret_stack_size = 4 veer: bht_size = 128 veer: bht_addr_lo = 4 veer: nmi_vec = 0x11110000 veer: lsu_stbuf_depth = 8 veer: lsu_num_nbload = 8 veer: fpga_optimize = 1 veer: dec_instbuf_depth = 4 veer: dma_buf_depth = 4 veer: reset_vec = 0x80000000 veer: btb_size = 128 veer: btb_index1_lo = 4 veer: btb_addr_lo = 4 veer: sb_bus_tag = 1 veer: dma_bus_tag = 1 veer: ifu_bus_tag = 3 veer: dccm_region = 0xf veer: dccm_offset = 0x40000 veer: dccm_size = 64 veer: dccm_num_banks = 8 veer: dccm_enable = 1 veer: pic_meigwctrl_count = 8 veer: pic_meigwclr_mask = 0x0 veer: pic_region = 0xf veer: pic_meip_mask = 0x0 veer: pic_meie_mask = 0x1 veer: pic_meigwctrl_offset = 0x4000 veer: pic_mpiccfg_count = 1 veer: pic_meigwclr_count = 8 veer: pic_offset = 0xc0000 veer: pic_meipl_mask = 0xf veer: pic_meipt_mask = 0x0 veer: pic_total_int = 8 veer: pic_meipt_count = 8 veer: pic_meipl_count = 8 veer: pic_mpiccfg_offset = 0x3000 veer: pic_meie_offset = 0x2000 veer: pic_meip_offset = 0x1000 veer: pic_meipt_offset = 0x3004 veer: pic_meipl_offset = 0x0000 veer: pic_mpiccfg_mask = 0x1 veer: pic_meip_count = 4 veer: pic_meie_count = 8 veer: pic_meigwctrl_mask = 0x3 veer: pic_size = 32 veer: pic_meigwclr_offset = 0x5000 veer: icache_tag_low = 6 veer: icache_enable = 1 veer: icache_size = 16 veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/common_defines.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/defines.h veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/pd_defines.vh veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/whisper.json veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/perl_configs.pl veer: Writing /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/snapshots/default/link.ld [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV [Pipeline] { [Pipeline] echo simulation not supported for System Verilog files [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/mem.sv Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dmi/dmi_jtag_to_core_sync.v Trying to read file: /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dmi/dmi_wrapper.v Cache-related signals in mem.sv Cache-related signals in dma_ctrl.sv Cache-related signals in veer_wrapper.sv Cache-related signals in veer.sv Cache-related signals in axi4_to_ahb.sv Cache-related signals in mem_lib.sv Cache-related signals in ahb_to_axi4.sv Cache-related signals in lsu.sv Cache-related signals in lsu_clkdomain.sv Cache-related signals in lsu_lsc_ctl.sv Cache-related signals in lsu_trigger.sv Cache-related signals in lsu_addrcheck.sv Cache-related signals in lsu_stbuf.sv Cache-related signals in lsu_bus_intf.sv Cache-related signals in lsu_dccm_ctl.sv Cache-related signals in lsu_bus_buffer.sv Cache-related signals in lsu_ecc.sv Cache-related signals in dec_ib_ctl.sv Cache-related signals in dec_decode_ctl.sv Cache-related signals in dec_tlu_ctl.sv Cache-related signals in dec.sv Cache-related signals in dbg.sv Cache-related signals in veer_types.sv Cache-related signals in ifu_mem_ctl.sv Cache-related signals in ifu_ifc_ctl.sv Cache-related signals in ifu_bp_ctl.sv Cache-related signals in ifu.sv Cache-related signals in ifu_aln_ctl.sv Cache-related signals in ifu_ic_mem.sv Cache-related signals in exu.sv Cache-related signals in exu_mul_ctl.sv Cache-related signals in exu_div_ctl.sv Cache-related signals in exu_alu_ctl.sv Results saved to /jenkins/processor_ci_utils/labels/Cores-SweRV.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Cores-SweRV -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Error executing Makefile. ERROR: [Synth 8-9263] cannot open include file 'pic_map_auto.h' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/pic_ctrl.sv:453] ERROR: [Synth 8-10157] use of undefined macro 'RV_DMA_BUS_TAG' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/dma_ctrl.sv:35] ERROR: [Synth 8-10157] use of undefined macro 'RV_PIC_TOTAL_INT_PLUS1' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:16] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:16] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BITS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:18] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:18] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BANK_BITS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:19] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:19] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_NUM_BANKS' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:20] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:20] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_DATA_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:21] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:21] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_FDATA_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:22] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:22] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_BYTE_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:23] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:23] ERROR: [Synth 8-10157] use of undefined macro 'RV_DCCM_ECC_WIDTH' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:24] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:24] ERROR: [Synth 8-10157] use of undefined macro 'RV_LSU_NUM_NBLOAD' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:26] ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/Cores-SweRV/Cores-SweRV/design/include/global.h:26] ERROR: [Synth 8-439] module 'processorci_top' not found ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 142, in <module> main( File "/eda/processor_ci/main.py", line 89, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 296, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: ac84a760-e504-4dc1-9d1a-cb81809179f0 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE