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Start of Pipeline - (3 hr 15 min in block)
node - (3 hr 15 min in block)
node block - (6 min 48 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (2.9 sec in block)
sh - (0.78 sec in self)rm -rf tinyriscv
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.91 sec in block)tinyriscv
dir block - (0.63 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)tinyriscv
dir block - (0.61 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6 min 40 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 40 sec in block)
parallel - (6 min 39 sec in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (11 sec in block)colorlight_i9
stage block (colorlight_i9) - (10 sec in block)
lock - (10 sec in block)colorlight_i9
lock block - (9.3 sec in block)
stage - (6.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (6.1 sec in block)
dir - (5.4 sec in block)tinyriscv
dir block - (5.1 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (4.5 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p tinyriscv -b colorlight_i9
stage - (0.96 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.39 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.39 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (6 min 39 sec in block)
stage - (6 min 38 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (6 min 38 sec in block)
lock - (6 min 37 sec in block)digilent_arty_a7_100t
lock block - (6 min 36 sec in block)
stage - (6 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (6 min 23 sec in block)
dir - (6 min 22 sec in block)tinyriscv
dir block - (6 min 22 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (6 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p tinyriscv -b digilent_arty_a7_100t
stage - (5.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.7 sec in block)
dir - (4.3 sec in block)tinyriscv
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p tinyriscv -b digilent_arty_a7_100t -l
stage - (7.3 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (7 sec in block)
echo - (0.21 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (6.5 sec in block)tinyriscv
dir block - (6.3 sec in block)
sh - (0.47 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.29 sec in self)**/*.xml