Console Output

+ iverilog -o simulation.out -g2012 -s scr1_core_top -I src/includes src/core/scr1_clk_ctrl.sv src/core/scr1_core_top.sv src/core/scr1_dm.sv src/core/scr1_dmi.sv src/core/scr1_scu.sv src/core/scr1_tapc.sv src/core/scr1_tapc_shift_reg.sv src/core/scr1_tapc_synchronizer.sv src/core/pipeline/scr1_ipic.sv src/core/pipeline/scr1_pipe_csr.sv src/core/pipeline/scr1_pipe_exu.sv src/core/pipeline/scr1_pipe_hdu.sv src/core/pipeline/scr1_pipe_ialu.sv src/core/pipeline/scr1_pipe_idu.sv src/core/pipeline/scr1_pipe_ifu.sv src/core/pipeline/scr1_pipe_lsu.sv src/core/pipeline/scr1_pipe_mprf.sv src/core/pipeline/scr1_pipe_tdu.sv src/core/pipeline/scr1_pipe_top.sv src/core/pipeline/scr1_tracelog.sv src/core/primitives/scr1_cg.sv src/core/primitives/scr1_reset_cells.sv
src/includes/scr1_arch_description.svh:124: syntax error
I give up.