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Start of Pipeline - (15 min in block)
node - (15 min in block)
node block - (11 min in block)
stage - (3.2 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.59 sec in self)rm -rf riscv
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/ultraembedded/riscv riscv
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.86 sec in block)riscv
dir block - (0.6 sec in block)
sh - (0.4 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s riscv_core -I core/riscv/ core/riscv/riscv_alu.v core/riscv/riscv_core.v core/riscv/riscv_csr.v core/riscv/riscv_csr_regfile.v core/riscv/riscv_decode.v core/riscv/riscv_decoder.v core/riscv/riscv_defs.v core/riscv/riscv_divider.v core/riscv/riscv_exec.v core/riscv/riscv_fetch.v core/riscv/riscv_issue.v core/riscv/riscv_lsu.v core/riscv/riscv_mmu.v core/riscv/riscv_multiplier.v core/riscv/riscv_pipe_ctrl.v core/riscv/riscv_regfile.v core/riscv/riscv_trace_sim.v core/riscv/riscv_xilinx_2r1w.v
stage - (1.9 sec in block)Utilities
stage block (Utilities) - (1.4 sec in block)
dir - (1 sec in block)riscv
dir block - (0.82 sec in block)
sh - (0.63 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (10 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (10 min in block)
parallel - (10 min in block)
parallel block (Branch: colorlight_i9) - (48 ms in block)
stage - (8 min 29 sec in block)colorlight_i9
stage block (colorlight_i9) - (8 min 28 sec in block)
lock - (8 min 28 sec in block)colorlight_i9
lock block - (4 min 43 sec in block)
stage - (4 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 23 sec in block)
dir - (4 min 22 sec in block)riscv
dir block - (4 min 22 sec in block)
echo - (0.18 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (4 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscv -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riscv
dir block - (15 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscv -b colorlight_i9 -l
stage - (2.3 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (2 sec in block)
echo - (0.22 sec in self)Testing FPGA colorlight_i9.
dir - (1.4 sec in block)riscv
dir block - (1.1 sec in block)
sh - (0.47 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (0.52 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
parallel block (Branch: digilent_arty_a7_100t) - (10 min in block)
stage - (10 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (10 min in block)
lock - (10 min in block)digilent_arty_a7_100t
lock block - (5 min 16 sec in block)
stage - (5 min 9 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)riscv
dir block - (5 min 7 sec in block)
echo - (0.3 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (5 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscv -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.3 sec in block)riscv
dir block - (4 sec in block)
echo - (0.17 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscv -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.9 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)riscv
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.41 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml