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Start of Pipeline - (2 min 46 sec in block)
node - (2 min 45 sec in block)
node block - (13 sec in block)
stage - (3.2 sec in block)Git Clone
stage block (Git Clone) - (2.7 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf riscv-atom
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/saursin/riscv-atom riscv-atom
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)riscv-atom
dir block - (0.66 sec in block)
sh - (0.44 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s AtomRV -I rtl/core/ rtl/core/Alu.v rtl/core/AtomRV.v rtl/core/AtomRV_wb.v rtl/core/CSR_Unit.v rtl/core/Decode.v rtl/core/RVC_Aligner.v rtl/core/RVC_Decoder.v rtl/core/RegisterFile.v
stage - (0.95 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (5.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 sec in block)
getContext - (0.26 sec in self)
parallel - (4.4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 sec in block)
stage - (3.5 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.2 sec in block)
getContext - (0.38 sec in self)
stage - (0.94 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.93 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.33 sec in block)
getContext - (0.15 sec in self)
stage - (0.68 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (1.1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.92 sec in block)
junit - (0.26 sec in self)**/*.xml