Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (5 min 7 sec in block)
node - (5 min 6 sec in block)
node block - (5 min 5 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (1.9 sec in block)
sh - (0.46 sec in self)rm -rf nerv
sh - (1.3 sec in self)git clone --recursive https://github.com/YosysHQ/nerv nerv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.88 sec in block)nerv
dir block - (0.6 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2012 -s nerv nerv.sv
stage - (4 min 59 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 58 sec in block)
parallel - (4 min 58 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (7.8 sec in block)colorlight_i9
stage block (colorlight_i9) - (7.5 sec in block)
lock - (6.6 sec in block)colorlight_i9
lock block - (5.9 sec in block)
stage - (3 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (2.4 sec in block)
dir - (1.7 sec in block)nerv
dir block - (1.2 sec in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (0.74 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b colorlight_i9
stage - (1.1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.43 sec in block)
getContext - (0.2 sec in self)
stage - (0.72 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.39 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (4 min 57 sec in block)
stage - (4 min 56 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (4 min 56 sec in block)
lock - (4 min 55 sec in block)digilent_nexys4_ddr
lock block - (4 min 55 sec in block)
stage - (4 min 38 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 38 sec in block)
dir - (4 min 37 sec in block)nerv
dir block - (4 min 37 sec in block)
echo - (0.18 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)nerv
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p nerv -b digilent_nexys4_ddr -l
stage - (1.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.97 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.41 sec in block)nerv
dir block - (0.15 sec in block)
stage - (1.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.5 sec in block)
dir - (1 sec in block)nerv
dir block - (0.75 sec in block)
sh - (0.53 sec in self)rm -rf *