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Start of Pipeline - (40 sec in block)
node - (39 sec in block)
node block - (25 sec in block)
stage - (15 sec in block)Git Clone
stage block (Git Clone) - (14 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.47 sec in self)rm -rf neorv32-verilog
sh - (13 sec in self)git clone --recursive --depth=1 https://github.com/stnolting/neorv32-verilog neorv32-verilog
stage - (2.6 sec in block)Simulation
stage block (Simulation) - (1.9 sec in block)
dir - (1.4 sec in block)neorv32-verilog
dir block - (1.1 sec in block)
sh - (0.93 sec in self)
stage - (0.92 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (5.9 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.3 sec in block)
getContext - (0.27 sec in self)
parallel - (4.6 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.2 sec in block)
stage - (3.8 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.5 sec in block)
getContext - (0.37 sec in self)
stage - (0.97 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (1.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.58 sec in block)
getContext - (0.37 sec in self)
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.27 sec in self)**/*.xml