Console Output

+ /eda/oss-cad-suite/bin/ghdl -a --std=2005 neorv32/rtl/core/neorv32_application_image.vhd neorv32/rtl/core/neorv32_boot_rom.vhd neorv32/rtl/core/neorv32_bootloader_image.vhd neorv32/rtl/core/neorv32_bus.vhd neorv32/rtl/core/neorv32_cache.vhd neorv32/rtl/core/neorv32_cfs.vhd neorv32/rtl/core/neorv32_clockgate.vhd neorv32/rtl/core/neorv32_cpu.vhd neorv32/rtl/core/neorv32_cpu_alu.vhd neorv32/rtl/core/neorv32_cpu_control.vhd neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd neorv32/rtl/core/neorv32_cpu_cp_cond.vhd neorv32/rtl/core/neorv32_cpu_cp_crypto.vhd neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd neorv32/rtl/core/neorv32_cpu_decompressor.vhd neorv32/rtl/core/neorv32_cpu_lsu.vhd neorv32/rtl/core/neorv32_cpu_pmp.vhd neorv32/rtl/core/neorv32_cpu_regfile.vhd neorv32/rtl/core/neorv32_crc.vhd neorv32/rtl/core/neorv32_debug_auth.vhd neorv32/rtl/core/neorv32_debug_dm.vhd neorv32/rtl/core/neorv32_debug_dtm.vhd neorv32/rtl/core/neorv32_dma.vhd neorv32/rtl/core/neorv32_dmem.vhd neorv32/rtl/core/neorv32_fifo.vhd neorv32/rtl/core/neorv32_gpio.vhd neorv32/rtl/core/neorv32_gptmr.vhd neorv32/rtl/core/neorv32_imem.vhd neorv32/rtl/core/neorv32_mtime.vhd neorv32/rtl/core/neorv32_neoled.vhd neorv32/rtl/core/neorv32_onewire.vhd neorv32/rtl/core/neorv32_package.vhd neorv32/rtl/core/neorv32_pwm.vhd neorv32/rtl/core/neorv32_sdi.vhd neorv32/rtl/core/neorv32_slink.vhd neorv32/rtl/core/neorv32_spi.vhd neorv32/rtl/core/neorv32_sys.vhd neorv32/rtl/core/neorv32_sysinfo.vhd neorv32/rtl/core/neorv32_top.vhd neorv32/rtl/core/neorv32_trng.vhd neorv32/rtl/core/neorv32_twd.vhd neorv32/rtl/core/neorv32_twi.vhd neorv32/rtl/core/neorv32_uart.vhd neorv32/rtl/core/neorv32_wdt.vhd neorv32/rtl/core/neorv32_xbus.vhd neorv32/rtl/core/neorv32_xip.vhd neorv32/rtl/core/neorv32_xirq.vhd neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd neorv32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd neorv32/rtl/system_integration/neorv32_litex_core_complex.vhd neorv32/rtl/system_integration/neorv32_vivado_ip.vhd neorv32/rtl/system_integration/xbus2ahblite_bridge.vhd neorv32/rtl/system_integration/xbus2axi4lite_bridge.vhd src/neorv32_verilog_wrapper.vhd sim/testbench.v sim/uart_sim_receiver.v neorv32/rtl/test_setups/neorv32_test_setup_approm.vhd neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd neorv32/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd neorv32/sim/neorv32_tb.vhd neorv32/sim/sim_uart_rx.vhd neorv32/sim/xbus_gateway.vhd neorv32/sim/xbus_memory.vhd
/eda/oss-cad-suite/libexec/ghdl:error: unknown language standard. Should be one of: 87, 93, 02, 08, 19