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Start of Pipeline - (26 min in block)
node - (26 min in block)
node block - (5 min 17 sec in block)
stage - (4.2 sec in block)Git Clone
stage block (Git Clone) - (3.7 sec in block)
sh - (0.57 sec in self)rm -rf *.xml
sh - (0.49 sec in self)rm -rf mriscv
sh - (2.3 sec in self)git clone --recursive --depth=1 https://github.com/onchipuis/mriscv mriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.85 sec in block)mriscv
dir block - (0.59 sec in block)
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.84 sec in block)mriscv
dir block - (0.59 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (5 min 8 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 7 sec in block)
parallel - (5 min 7 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (5 min 6 sec in block)
stage - (5 min 6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 6 sec in block)
lock - (5 min 6 sec in block)digilent_arty_a7_100t
lock block - (5 min 5 sec in block)
stage - (4 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 52 sec in block)
dir - (4 min 52 sec in block)mriscv
dir block - (4 min 52 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (4 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p mriscv -b digilent_arty_a7_100t
stage - (5 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)mriscv
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p mriscv -b digilent_arty_a7_100t -l
stage - (6.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (6.4 sec in block)
echo - (0.16 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.77 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.28 sec in self)**/*.xml