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Start of Pipeline - (57 sec in block)
node - (56 sec in block)
node block - (55 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (2.9 sec in block)
sh - (0.46 sec in self)rm -rf mriscv
sh - (2.2 sec in self)git clone --recursive --depth=1 https://github.com/onchipuis/mriscv mriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.88 sec in block)mriscv
dir block - (0.62 sec in block)
sh - (0.4 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s mriscvcore mriscvcore/mriscvcore.v mriscvcore/ALU/ALU.v mriscvcore/DECO_INSTR/DECO_INSTR.v mriscvcore/FSM/FSM.v mriscvcore/IRQ/IRQ.v mriscvcore/MEMORY_INTERFACE/MEMORY_INTERFACE.v mriscvcore/MULT/MULT.v mriscvcore/REG_FILE/REG_FILE.v mriscvcore/UTILITIES/UTILITY.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)mriscv
dir block - (0.62 sec in block)
sh - (0.42 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (47 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (47 sec in block)
parallel - (46 sec in block)
parallel block (Branch: colorlight_i9) - (52 ms in block)
stage - (7 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.7 sec in block)
lock - (6 sec in block)colorlight_i9
lock block - (5.3 sec in block)
stage - (2.8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.2 sec in block)
dir - (1.5 sec in block)mriscv
dir block - (1.1 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.65 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b colorlight_i9
stage - (0.97 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.7 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.37 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (46 sec in block)
stage - (45 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (45 sec in block)
lock - (44 sec in block)digilent_arty_a7_100t
lock block - (43 sec in block)
stage - (41 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (40 sec in block)
dir - (39 sec in block)mriscv
dir block - (39 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (39 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mriscv -b digilent_arty_a7_100t
stage - (0.93 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.69 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.73 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.51 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml