Console Output

+ /eda/oss-cad-suite/bin/ghdl -a --std=08 Project/Components/ALU.vhd Project/Components/EX_MEM_DIV.vhd Project/Components/ID_EX_DIV.vhd Project/Components/IF_ID_DIV.vhd Project/Components/MEM_WB_DIV.vhd Project/Components/adder.vhd Project/Components/controller.vhd Project/Components/datapath.vhd Project/Components/flushing_unit.vhd Project/Components/forwarding_unit.vhd Project/Components/jump_target_unit.vhd Project/Components/mux_2_1.vhd Project/Components/mux_32_1.vhd Project/Components/mux_3_1.vhd Project/Components/mux_5_1.vhd Project/Components/progmem_interface.vhd Project/Components/program_counter.vhd Project/Components/reg1b.vhd Project/Components/reg2b.vhd Project/Components/reg32b.vhd Project/Components/reg32b_falling_edge.vhd Project/Components/reg3b.vhd Project/Components/reg4b.vhd Project/Components/reg5b.vhd Project/Components/register_file.vhd
Project/Components/EX_MEM_DIV.vhd:89:27:error: no declaration for "reg3b"
        data_format_reg : reg3b port map(data_format_input_signal, '1', clock, clear, data_format_output_signal);
                          ^
Project/Components/EX_MEM_DIV.vhd:90:29:error: no declaration for "reg1b"
        datamem_write_reg : reg1b port map(datamem_write_input_signal, '1', clock, clear, datamem_write_output_signal);
                            ^
Project/Components/EX_MEM_DIV.vhd:91:25:error: no declaration for "reg1b"
        jump_flag_reg : reg1b port map(jump_flag_input_signal, '1', clock, clear, jump_flag_output_signal);
                        ^
Project/Components/EX_MEM_DIV.vhd:94:24:error: no declaration for "reg2b"
        mux0_sel_reg : reg2b port map(mux0_sel_input_signal, '1', clock, clear, mux0_sel_output_signal);
                       ^
Project/Components/EX_MEM_DIV.vhd:95:30:error: no declaration for "reg1b"
        reg_file_write_reg : reg1b port map(reg_file_write_input_signal, '1', clock, clear, reg_file_write_output_signal);
                             ^
Project/Components/EX_MEM_DIV.vhd:96:38:error: no declaration for "reg5b"
        reg_file_write_address_reg : reg5b port map(reg_file_write_address_input_signal, '1', clock, clear, reg_file_write_address_output_signal);
                                     ^
Project/Components/EX_MEM_DIV.vhd:99:26:error: no declaration for "reg32b"
        ALU_output_reg : reg32b port map(ALU_output_input_signal, '1', clock, clear, ALU_output_output_signal);
                         ^
Project/Components/EX_MEM_DIV.vhd:100:38:error: no declaration for "reg32b"
        register_file_output_1_reg : reg32b port map(register_file_output_1_input_signal, '1', clock, clear, register_file_output_1_output_signal);
                                     ^
Project/Components/EX_MEM_DIV.vhd:101:34:error: no declaration for "reg1b"
        ALU_branch_respose_reg : reg1b port map(ALU_branch_response_input_signal, '1', clock, clear, ALU_branch_response_output_signal);
                                 ^
Project/Components/EX_MEM_DIV.vhd:102:35:error: no declaration for "reg32b"
        instruction_address_reg : reg32b port map(instruction_address_input_signal, '1', clock, clear, instruction_address_output_signal);
                                  ^
/eda/oss-cad-suite/libexec/ghdl:error: compilation error