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Start of Pipeline - (28 sec in block)
node - (24 sec in block)
node block - (22 sec in block)
stage - (9.4 sec in block)Git Clone
stage block (Git Clone) - (8.2 sec in block)
sh - (2.6 sec in self)rm -rf *.xml
sh - (0.68 sec in self)rm -rf SuperScalar-RISCV-CPU
sh - (2.2 sec in self)git clone --recursive --depth=1 https://github.com/risclite/SuperScalar-RISCV-CPU SuperScalar-RISCV-CPU
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (1 sec in block)SuperScalar-RISCV-CPU
dir block - (0.72 sec in block)
sh - (0.49 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s ssrv_top -I rtl/ rtl/alu.v rtl/define.v rtl/define_para.v rtl/include_func.v rtl/instrbits.v rtl/instrman.v rtl/lsu.v rtl/membuf.v rtl/mprf.v rtl/mul.v rtl/predictor.v rtl/schedule.v rtl/ssrv_top.v rtl/sys_csr.v
stage - (1 sec in block)Utilities
stage block (Utilities) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (5.7 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.2 sec in block)
getContext - (0.26 sec in self)
parallel - (4.5 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.1 sec in block)
stage - (3.7 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.4 sec in block)
getContext - (0.39 sec in self)
stage - (0.99 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.97 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.67 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.26 sec in self)**/*.xml