Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s riftChip -I RiftChip RiftChip/riftChip.v RiftChip/axi/axi_full_mst.v RiftChip/axi/axi_full_slv.v RiftChip/axi/axi_lite_mst.v RiftChip/axi/axi_lite_slv.v RiftChip/axi/AXI BUS TEMPLE/axi4_full_master.v RiftChip/axi/AXI BUS TEMPLE/axi4_full_slave.v RiftChip/axi/AXI BUS TEMPLE/axi4_lite_master.v RiftChip/axi/AXI BUS TEMPLE/axi4_lite_slave.v RiftChip/debug/DM.v RiftChip/debug/DMI.v RiftChip/debug/DTM.v RiftChip/debug/core_monitor.v RiftChip/element/gen_asymmetricFIFO.v RiftChip/element/gen_bypassfifo.v RiftChip/element/gen_counter.v RiftChip/element/gen_csrreg.v RiftChip/element/gen_dffr.v RiftChip/element/gen_dffren.v RiftChip/element/gen_dpdffren.v RiftChip/element/gen_fifo.v RiftChip/element/gen_ppbuff.v RiftChip/element/gen_ringStack.v RiftChip/element/gen_rsffr.v RiftChip/element/gen_slffr.v RiftChip/element/gen_sram.v RiftChip/element/gen_suffr.v RiftChip/element/gen_syn.v RiftChip/element/lfsr.v RiftChip/element/lzp.v RiftChip/riftCore/backEnd.v RiftChip/riftCore/frontEnd.v RiftChip/riftCore/instr_fifo.v RiftChip/riftCore/riftCore.v RiftChip/riftCore/backend/commit.v RiftChip/riftCore/backend/csrFiles.v RiftChip/riftCore/backend/dispatch.v RiftChip/riftCore/backend/phyRegister.v RiftChip/riftCore/backend/regFiles.v RiftChip/riftCore/backend/rename.v RiftChip/riftCore/backend/writeBack.v RiftChip/riftCore/backend/execute/alu.v RiftChip/riftCore/backend/execute/bru.v RiftChip/riftCore/backend/execute/csr.v RiftChip/riftCore/backend/execute/lsu.v RiftChip/riftCore/backend/execute/mul.v RiftChip/riftCore/backend/issue/alu_issue.v RiftChip/riftCore/backend/issue/bru_issue.v RiftChip/riftCore/backend/issue/csr_issue.v RiftChip/riftCore/backend/issue/issue_buffer.v RiftChip/riftCore/backend/issue/issue_fifo.v RiftChip/riftCore/backend/issue/lsu_issue.v RiftChip/riftCore/backend/issue/mul_issue.v RiftChip/riftCore/cache/L2cache.v RiftChip/riftCore/cache/L3cache.v RiftChip/riftCore/cache/cache.v RiftChip/riftCore/cache/cache_mem.v RiftChip/riftCore/cache/dirty_block.v RiftChip/riftCore/cache/wt_block.v RiftChip/riftCore/frontend/branch_predict.v RiftChip/riftCore/frontend/decoder.v RiftChip/riftCore/frontend/decoder16.v RiftChip/riftCore/frontend/decoder32.v RiftChip/riftCore/frontend/iAlign.v RiftChip/riftCore/frontend/icache.v RiftChip/riftCore/frontend/iqueue.v RiftChip/riftCore/frontend/pcGenerate.v RiftChip/riftCore/frontend/preDecode.v
RiftChip/axi/AXI: No such file or directory
RiftChip/axi/axi_full_mst.v:114: syntax error
RiftChip/axi/axi_full_mst.v:114: error: Syntax error in continuous assignment
RiftChip/axi/axi_full_mst.v:125: syntax error
RiftChip/axi/axi_full_mst.v:125: error: Syntax error in continuous assignment
RiftChip/axi/axi_full_mst.v:135: syntax error
RiftChip/axi/axi_full_mst.v:135: error: Syntax error in continuous assignment
RiftChip/axi/axi_full_slv.v:34: syntax error
RiftChip/axi/axi_full_slv.v:34: Errors in port declarations.
RiftChip/axi/axi_full_slv.v:39: syntax error
I give up.