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Start of Pipeline - (4 min 47 sec in block)
node - (4 min 46 sec in block)
node block - (4 min 42 sec in block)
stage - (3.5 sec in block)Git Clone
stage block (Git Clone) - (3 sec in block)
sh - (0.59 sec in self)rm -rf Grande-Risco-5
sh - (1.8 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.97 sec in block)
dir - (0.58 sec in block)Grande-Risco-5
dir block - (0.32 sec in block)
echo - (0.11 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.88 sec in block)Grande-Risco-5
dir block - (0.6 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (4 min 34 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 33 sec in block)
parallel - (4 min 33 sec in block)
parallel block (Branch: colorlight_i9) - (52 ms in block)
stage - (4 min 31 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 30 sec in block)
lock - (4 min 29 sec in block)colorlight_i9
lock block - (4 min 28 sec in block)
stage - (4 min 24 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 23 sec in block)
dir - (4 min 22 sec in block)Grande-Risco-5
dir block - (4 min 22 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (4 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9
stage - (1.8 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.63 sec in block)
getContext - (0.16 sec in self)
stage - (1.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.62 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (4 min 32 sec in block)
stage - (4 min 31 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 min 31 sec in block)
lock - (4 min 30 sec in block)digilent_arty_a7_100t
lock block - (4 min 28 sec in block)
stage - (4 min 24 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 23 sec in block)
dir - (4 min 23 sec in block)Grande-Risco-5
dir block - (4 min 22 sec in block)
echo - (0.18 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (4 min 22 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t
stage - (1.8 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.75 sec in block)
getContext - (0.17 sec in self)
stage - (1.4 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.65 sec in block)
getContext - (0.16 sec in self)
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.27 sec in self)**/*.xml