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Start of Pipeline - (10 min in block)
node - (10 min in block)
node block - (10 min in block)
stage - (3 sec in block)Git Clone
stage block (Git Clone) - (2.5 sec in block)
sh - (0.46 sec in self)rm -rf Grande-Risco-5
sh - (1.8 sec in self)git clone --recursive --depth=1 https://github.com/JN513/Grande-Risco-5 Grande-Risco-5
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.96 sec in block)
dir - (0.55 sec in block)Grande-Risco-5
dir block - (0.3 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.2 sec in block)Utilities
stage block (Utilities) - (0.77 sec in block)
dir - (0.39 sec in block)Grande-Risco-5
dir block - (0.14 sec in block)
stage - (10 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (10 min in block)
parallel - (10 min in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (10 min in block)colorlight_i9
stage block (colorlight_i9) - (10 min in block)
lock - (10 min in block)colorlight_i9
lock block - (10 min in block)
stage - (10 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (10 min in block)
dir - (10 min in block)Grande-Risco-5
dir block - (10 min in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (10 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9
stage - (19 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (19 sec in block)
dir - (19 sec in block)Grande-Risco-5
dir block - (18 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (18 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b colorlight_i9 -l
stage - (2.1 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.9 sec in block)
echo - (0.21 sec in self)Testing FPGA colorlight_i9.
dir - (1.3 sec in block)Grande-Risco-5
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (0.39 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
parallel block (Branch: digilent_arty_a7_100t) - (10 min in block)
stage - (10 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (10 min in block)
lock - (10 min in block)digilent_arty_a7_100t
lock block - (10 min in block)
stage - (9 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (9 min 53 sec in block)
dir - (9 min 52 sec in block)Grande-Risco-5
dir block - (9 min 52 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (9 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t
stage - (5.4 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.9 sec in block)
dir - (4.5 sec in block)Grande-Risco-5
dir block - (4.2 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p Grande-Risco-5 -b digilent_arty_a7_100t -l
stage - (2.2 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.9 sec in block)
echo - (0.2 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)Grande-Risco-5
dir block - (1.1 sec in block)
sh - (0.47 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.4 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.75 sec in block)
junit - (0.48 sec in self)**/test-reports/*.xml