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Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/F03x [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf F03x [Pipeline] sh + git clone --recursive --depth=1 https://github.com/klessydra/F03x F03x Cloning into 'F03x'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/F03x/F03x [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/ghdl -a --std=08 klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd klessydra-f0-3th/PKG_RiscV_Klessydra.vhd klessydra-f0-3th/TMR_REG_PKG.vhd klessydra-f0-3th/CMP-TMR_REG.vhd klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd klessydra-f0-3th/RTL-Debug_Unit.vhd klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd klessydra-f0-3th/STR-Klessydra_top.vhd klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:129:12:warning: declaration of "taken_branch" hides port "taken_branch" [-Whide] signal taken_branch : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:130:12:warning: declaration of "wfi_condition_pending" hides signal "wfi_condition_pending" [-Whide] signal wfi_condition_pending : out std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:131:12:warning: declaration of "set_wfi_condition" hides port "set_wfi_condition" [-Whide] signal set_wfi_condition : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:132:12:warning: declaration of "taken_branch_pending" hides port "taken_branch_pending" [-Whide] signal taken_branch_pending : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:133:16:warning: declaration of "taken_branch_pending_wire" hides signal "taken_branch_pending_wire" [-Whide] signal taken_branch_pending_wire : out std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:134:12:warning: declaration of "set_except_condition" hides port "set_except_condition" [-Whide] signal set_except_condition : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:135:12:warning: declaration of "set_mret_condition" hides port "set_mret_condition" [-Whide] signal set_mret_condition : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:136:12:warning: declaration of "pc" hides signal "pc" [-Whide] signal pc : out std_logic_vector(31 downto 0); ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:137:12:warning: declaration of "taken_branch_pc_lat" hides port "taken_branch_pc_lat" [-Whide] signal taken_branch_pc_lat : in std_logic_vector(31 downto 0); ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:138:12:warning: declaration of "incremented_pc" hides port "incremented_pc" [-Whide] signal incremented_pc : in std_logic_vector(31 downto 0); ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:139:12:warning: declaration of "boot_pc" hides signal "boot_pc" [-Whide] signal boot_pc : in std_logic_vector(31 downto 0); ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:140:12:warning: declaration of "pc_update_enable" hides signal "pc_update_enable" [-Whide] signal pc_update_enable : in std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:141:12:warning: declaration of "served_except_condition" hides port "served_except_condition" [-Whide] signal served_except_condition : out std_logic; ^ klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd:142:12:warning: declaration of "served_mret_condition" hides port "served_mret_condition" [-Whide] signal served_mret_condition : out std_logic) is ^ [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/F03x/F03x [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/F03x/F03x -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels WARNING: No LICENSE files found. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] Resource [digilent_arty_a7_100t] did not exist. Created. Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/F03x/F03x [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/F03x/F03x [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p F03x -b colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/F03x/F03x/build_colorlight_i9.tcl Error executing Makefile. ERROR: TCL interpreter returned an error: Yosys command produced an error make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p F03x -b digilent_arty_a7_100t [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/F03x/F03x/build_digilent_arty_a7_100t.tcl Error executing Makefile. ERROR: [Common 17-69] Command failed: File '/eda/processor-ci-controller/modules/uart.v' does not exist make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 307, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 7e1df127-2bde-4f9a-8eb0-d5bbecda9a40 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE