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+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p F03x -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/F03x/F03x/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
ERROR: [Synth 8-2757] this construct is only supported in VHDL 1076-2008 [/var/lib/jenkins/workspace/F03x/F03x/klessydra-f0-3th/CMP-TMR_REG.vhd:89]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.