Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (20 min in block)
node - (20 min in block)
node block - (20 min in block)
stage - (3.1 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.7 sec in self)rm -rf DV-CPU-RV
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.91 sec in block)DV-CPU-RV
dir block - (0.65 sec in block)
sh - (0.43 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.9 sec in block)DV-CPU-RV
dir block - (0.65 sec in block)
sh - (0.43 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (20 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (20 min in block)
parallel - (20 min in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (4 min 34 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 34 sec in block)
lock - (4 min 33 sec in block)colorlight_i9
lock block - (5 sec in block)
stage - (2.8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2.1 sec in block)
dir - (1.4 sec in block)DV-CPU-RV
dir block - (1 sec in block)
echo - (0.2 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (0.47 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p DV-CPU-RV -b colorlight_i9
stage - (0.96 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (0.68 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.38 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (20 min in block)
stage - (20 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (20 min in block)
lock - (20 min in block)digilent_arty_a7_100t
lock block - (5 min 16 sec in block)
stage - (5 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)DV-CPU-RV
dir block - (5 min 7 sec in block)
echo - (0.31 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (5 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p DV-CPU-RV -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)DV-CPU-RV
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p DV-CPU-RV -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.8 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)DV-CPU-RV
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.4 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (0.8 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml