Console Output

+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p AUK-V-Aethia -b digilent_nexys4_ddr -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/AUK-V-Aethia/AUK-V-Aethia/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Parse file DONE
Erase SRAM Load SRAM 
Load SRAM: [======                                            ] 10.28%
Load SRAM: [===========                                       ] 20.56%
Load SRAM: [================                                  ] 30.83%
Load SRAM: [====================                              ] 39.40%
Load SRAM: [=========================                         ] 49.68%
Load SRAM: [==============================                    ] 58.24%
Load SRAM: [=================================                 ] 65.09%
Load SRAM: [======================================            ] 75.37%
Load SRAM: [==========================================        ] 83.93%
Load SRAM: [===============================================   ] 92.50%
Load SRAM: [===================================================] 100.00%
Done
DONE