Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/simodense
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf *.xml
[Pipeline] sh
+ rm -rf simodense
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/pphilippos/simodense simodense
Cloning into 'simodense'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/simodense/simodense
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s Core RTL_and_simulation/cpu.v
RTL_and_simulation/cpu.v:134: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:196: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:235: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:255: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:259: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:264: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:490: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:501: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:509: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:516: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:517: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:524: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:531: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:545: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:550: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:556: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:566: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:567: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:573: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:577: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:588: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:594: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:627: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:632: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:640: warning: macro STDO undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:662: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:666: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:679: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:710: warning: macro DEB undefined (and assumed null) at this point.
RTL_and_simulation/cpu.v:134: syntax error
RTL_and_simulation/cpu.v:134: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:196: syntax error
RTL_and_simulation/cpu.v:196: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:235: syntax error
RTL_and_simulation/cpu.v:235: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:255: syntax error
RTL_and_simulation/cpu.v:255: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:259: syntax error
RTL_and_simulation/cpu.v:259: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:264: syntax error
RTL_and_simulation/cpu.v:264: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:490: syntax error
RTL_and_simulation/cpu.v:490: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:501: syntax error
RTL_and_simulation/cpu.v:501: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:509: syntax error
RTL_and_simulation/cpu.v:509: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:516: syntax error
RTL_and_simulation/cpu.v:516: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:517: syntax error
RTL_and_simulation/cpu.v:517: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:524: syntax error
RTL_and_simulation/cpu.v:524: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:531: syntax error
RTL_and_simulation/cpu.v:531: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:545: syntax error
RTL_and_simulation/cpu.v:545: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:550: syntax error
RTL_and_simulation/cpu.v:550: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:556: syntax error
RTL_and_simulation/cpu.v:556: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:566: syntax error
RTL_and_simulation/cpu.v:566: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:567: syntax error
RTL_and_simulation/cpu.v:567: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:573: syntax error
RTL_and_simulation/cpu.v:573: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:577: syntax error
RTL_and_simulation/cpu.v:577: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:588: syntax error
RTL_and_simulation/cpu.v:588: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:594: syntax error
RTL_and_simulation/cpu.v:594: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:627: syntax error
RTL_and_simulation/cpu.v:627: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:632: syntax error
RTL_and_simulation/cpu.v:632: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:640: syntax error
RTL_and_simulation/cpu.v:640: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:662: syntax error
RTL_and_simulation/cpu.v:662: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:666: syntax error
RTL_and_simulation/cpu.v:666: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:679: syntax error
RTL_and_simulation/cpu.v:679: error: Malformed conditional expression.
RTL_and_simulation/cpu.v:710: syntax error
RTL_and_simulation/cpu.v:710: error: Malformed conditional expression.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: digilent_arty_a7_100t)
[Pipeline] stage
[Pipeline] { (digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_arty_a7_100t)
Stage "digilent_arty_a7_100t" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_arty_a7_100t
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 94e44c63-1ff9-438e-a7c7-32816f74dd7e
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:49)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 58
Finished: FAILURE