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Start of Pipeline - (10 min in block)
node - (10 min in block)
node block - (10 min in block)
stage - (3.7 sec in block)Git Clone
stage block (Git Clone) - (3.2 sec in block)
sh - (0.65 sec in self)rm -rf serv
sh - (2.2 sec in self)git clone --recursive https://github.com/olofk/serv serv
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)serv
dir block - (0.6 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v
stage - (10 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (10 min in block)
parallel - (10 min in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (4 min 25 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 24 sec in block)
lock - (4 min 23 sec in block)colorlight_i9
lock block - (4 min 0 sec in block)
stage - (3 min 38 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (3 min 38 sec in block)
dir - (3 min 37 sec in block)serv
dir block - (3 min 37 sec in block)
echo - (0.33 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (3 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b colorlight_i9
stage - (13 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (13 sec in block)
dir - (13 sec in block)serv
dir block - (12 sec in block)
echo - (0.14 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b colorlight_i9 -l
stage - (6.6 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6.2 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.6 sec in block)serv
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (10 min in block)
stage - (10 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (10 min in block)
lock - (10 min in block)digilent_nexys4_ddr
lock block - (4 min 54 sec in block)
stage - (4 min 39 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 38 sec in block)
dir - (4 min 37 sec in block)serv
dir block - (4 min 37 sec in block)
echo - (0.42 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (4 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b digilent_nexys4_ddr
stage - (13 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)serv
dir block - (12 sec in block)
echo - (0.16 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p serv -b digilent_nexys4_ddr -l
stage - (1.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.96 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.41 sec in block)serv
dir block - (0.15 sec in block)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.77 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml