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Start of Pipeline - (3 min 48 sec in block)
node - (3 min 47 sec in block)
node block - (13 sec in block)
stage - (3.2 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.56 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf serv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/olofk/serv serv
stage - (2 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.96 sec in block)serv
dir block - (0.64 sec in block)
sh - (0.44 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v
stage - (0.93 sec in block)Utilities
stage block (Utilities) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (5.9 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.3 sec in block)
getContext - (0.27 sec in self)
parallel - (4.7 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.3 sec in block)
stage - (3.9 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.6 sec in block)
getContext - (0.38 sec in self)
stage - (1.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.92 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.26 sec in self)**/*.xml