Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v
rtl/serv_state.v:105: error: Unable to bind wire/reg/memory `trap_pending' in `serv_top.state'
rtl/serv_state.v:217:      : A symbol with that name was declared here. Check for declaration after use.
rtl/serv_state.v:103: error: Unable to elaborate r-value: (((((i_shift_op)&((i_sh_right)?((i_sh_done)&((last_init)|((!(o_cnt_en))&(init_done)))):(last_init)))|(i_dbus_ack))|((MDU)&(i_mdu_ready)))|((i_branch_op)&((last_init)&(!(trap_pending)))))|(((i_rd_alu_en)&(i_alu_rd_sel1))&(last_init))
rtl/serv_state.v:112: error: Unable to bind wire/reg/memory `trap_pending' in `serv_top.state'
rtl/serv_state.v:217:      : A symbol with that name was declared here. Check for declaration after use.
rtl/serv_state.v:112: error: Unable to elaborate r-value: (i_ibus_ack)|((trap_pending)&(last_init))
4 error(s) during elaboration.