Start of Pipeline - (3 min 10 sec in block) | | | |
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node - (3 min 9 sec in block) | | | |
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node block - (3 min 9 sec in block) | | | |
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stage - (41 sec in block) | Git Clone | | |
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stage block (Git Clone) - (40 sec in block) | | | |
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sh - (0.47 sec in self) | rm -rf *.xml | | |
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sh - (0.97 sec in self) | rm -rf scr1 | | |
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sh - (39 sec in self) | git clone --recursive --depth=1 https://github.com/syntacore/scr1 scr1 | | |
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stage - (1.4 sec in block) | Simulation | | |
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stage block (Simulation) - (0.91 sec in block) | | | |
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dir - (0.53 sec in block) | scr1 | | |
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dir block - (0.3 sec in block) | | | |
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echo - (0.1 sec in self) | simulation not supported for System Verilog files | | |
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stage - (1.7 sec in block) | Utilities | | |
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stage block (Utilities) - (1.2 sec in block) | | | |
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dir - (0.89 sec in block) | scr1 | | |
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dir block - (0.62 sec in block) | | | |
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sh - (0.41 sec in self) | python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels | | |
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stage - (2 min 23 sec in block) | FPGA Build Pipeline | | |
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stage block (FPGA Build Pipeline) - (2 min 23 sec in block) | | | |
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parallel - (2 min 22 sec in block) | | | |
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parallel block (Branch: digilent_arty_a7_100t) - (2 min 22 sec in block) | | | |
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stage - (2 min 22 sec in block) | digilent_arty_a7_100t | | |
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stage block (digilent_arty_a7_100t) - (2 min 21 sec in block) | | | |
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lock - (2 min 21 sec in block) | digilent_arty_a7_100t | | |
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lock block - (2 min 20 sec in block) | | | |
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stage - (2 min 8 sec in block) | Synthesis and PnR | | |
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stage block (Synthesis and PnR) - (2 min 8 sec in block) | | | |
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dir - (2 min 7 sec in block) | scr1 | | |
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dir block - (2 min 7 sec in block) | | | |
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echo - (0.57 sec in self) | Starting synthesis for FPGA digilent_arty_a7_100t. | | |
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sh - (2 min 6 sec in self) | python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p scr1 -b digilent_arty_a7_100t | | |
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stage - (5.1 sec in block) | Flash digilent_arty_a7_100t | | |
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stage block (Flash digilent_arty_a7_100t) - (4.7 sec in block) | | | |
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dir - (4.2 sec in block) | scr1 | | |
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dir block - (4 sec in block) | | | |
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echo - (0.16 sec in self) | Flashing FPGA digilent_arty_a7_100t. | | |
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sh - (3.6 sec in self) | python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p scr1 -b digilent_arty_a7_100t -l | | |
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stage - (6.7 sec in block) | Test digilent_arty_a7_100t | | |
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stage block (Test digilent_arty_a7_100t) - (6.4 sec in block) | | | |
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echo - (0.17 sec in self) | Testing FPGA digilent_arty_a7_100t. | | |
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sh - (0.47 sec in self) | echo "Test for FPGA in /dev/ttyUSB1" | | |
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sh - (5.6 sec in self) | python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 | | |
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stage - (0.91 sec in block) | Declarative: Post Actions | | |
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stage block (Declarative: Post Actions) - (0.65 sec in block) | | | |
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junit - (0.37 sec in self) | **/*.xml | | |
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