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Start of Pipeline - (2 min 25 sec in block)
node - (2 min 24 sec in block)
node block - (2 min 23 sec in block)
stage - (1 min 3 sec in block)Git Clone
stage block (Git Clone) - (1 min 2 sec in block)
sh - (1 sec in self)rm -rf scr1
sh - (1 min 1 sec in self)git clone --recursive --depth=1 https://github.com/syntacore/scr1 scr1
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.94 sec in block)
dir - (0.56 sec in block)scr1
dir block - (0.32 sec in block)
echo - (0.1 sec in self)simulation not supported for System Verilog files
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.83 sec in block)scr1
dir block - (0.59 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (1 min 16 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (1 min 15 sec in block)
parallel - (1 min 15 sec in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (28 sec in block)colorlight_i9
stage block (colorlight_i9) - (28 sec in block)
lock - (27 sec in block)colorlight_i9
lock block - (26 sec in block)
stage - (24 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (23 sec in block)
dir - (23 sec in block)scr1
dir block - (22 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (22 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p scr1 -b colorlight_i9
stage - (0.94 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.37 sec in block)
getContext - (0.17 sec in self)
stage - (0.67 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.38 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_arty_a7_100t) - (1 min 14 sec in block)
stage - (1 min 14 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (1 min 13 sec in block)
lock - (1 min 13 sec in block)digilent_arty_a7_100t
lock block - (1 min 12 sec in block)
stage - (1 min 10 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 9 sec in block)
dir - (1 min 8 sec in block)scr1
dir block - (1 min 8 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p scr1 -b digilent_arty_a7_100t
stage - (0.94 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.79 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.3 sec in self)**/test-reports/*.xml