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Start of Pipeline - (1 min 11 sec in block)
node - (1 min 10 sec in block)
node block - (1 min 10 sec in block)
stage - (56 sec in block)Git Clone
stage block (Git Clone) - (55 sec in block)
sh - (0.46 sec in self)rm -rf scr1
sh - (55 sec in self)git clone --recursive --depth=1 https://github.com/syntacore/scr1 scr1
stage - (2.5 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.98 sec in block)scr1
dir block - (0.68 sec in block)
sh - (0.47 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s scr1_core_top -I src/includes src/core/scr1_clk_ctrl.sv src/core/scr1_core_top.sv src/core/scr1_dm.sv src/core/scr1_dmi.sv src/core/scr1_scu.sv src/core/scr1_tapc.sv src/core/scr1_tapc_shift_reg.sv src/core/scr1_tapc_synchronizer.sv src/core/pipeline/scr1_ipic.sv src/core/pipeline/scr1_pipe_csr.sv src/core/pipeline/scr1_pipe_exu.sv src/core/pipeline/scr1_pipe_hdu.sv src/core/pipeline/scr1_pipe_ialu.sv src/core/pipeline/scr1_pipe_idu.sv src/core/pipeline/scr1_pipe_ifu.sv src/core/pipeline/scr1_pipe_lsu.sv src/core/pipeline/scr1_pipe_mprf.sv src/core/pipeline/scr1_pipe_tdu.sv src/core/pipeline/scr1_pipe_top.sv src/core/pipeline/scr1_tracelog.sv src/core/primitives/scr1_cg.sv src/core/primitives/scr1_reset_cells.sv
stage - (0.95 sec in block)Utilities
stage block (Utilities) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (9.2 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (8.7 sec in block)
getContext - (0.27 sec in self)
parallel - (8 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (6.5 sec in block)colorlight_i9
stage block (colorlight_i9) - (6.1 sec in block)
getContext - (0.66 sec in self)
stage - (1.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.62 sec in block)
getContext - (0.17 sec in self)
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.59 sec in block)
getContext - (0.15 sec in self)
stage - (1.1 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.58 sec in block)
getContext - (0.15 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (7.4 sec in block)
stage - (6.5 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6 sec in block)
getContext - (0.64 sec in self)
stage - (1.7 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.7 sec in block)
getContext - (0.15 sec in self)
stage - (1.7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.69 sec in block)
getContext - (0.17 sec in self)
stage - (1.1 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.69 sec in block)
getContext - (0.15 sec in self)
stage - (0.75 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.28 sec in self)**/test-reports/*.xml