Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rvsteel_core hardware/rvsteel_core.v
hardware/rvsteel_core.v: No such file or directory
error: Unable to find the root module "Segmentation fault (core dumped)
rvsteel_core" in the Verilog source.
     : Perhaps ``-s rvsteel_core'' is incorrect?
1 error(s) during elaboration.