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Start of Pipeline - (3 min 22 sec in block)
node - (3 min 21 sec in block)
node block - (2 min 31 sec in block)
stage - (3.6 sec in block)Git Clone
stage block (Git Clone) - (3.1 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf rv3n
sh - (1.6 sec in self)git clone --recursive --depth=1 https://github.com/risclite/rv3n rv3n
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.89 sec in block)rv3n
dir block - (0.63 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s rv3n_top -I rtl rtl/define.v rtl/define_para.v rtl/include_func.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)rv3n
dir block - (0.61 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (2 min 22 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (2 min 22 sec in block)
parallel - (2 min 22 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (2 min 21 sec in block)
stage - (2 min 21 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (2 min 21 sec in block)
lock - (2 min 20 sec in block)digilent_arty_a7_100t
lock block - (2 min 20 sec in block)
stage - (2 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2 min 7 sec in block)
dir - (2 min 7 sec in block)rv3n
dir block - (2 min 7 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (2 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rv3n -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)rv3n
dir block - (3.9 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rv3n -b digilent_arty_a7_100t -l
stage - (6.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (6.4 sec in block)
echo - (0.15 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.79 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.57 sec in block)
junit - (0.3 sec in self)**/*.xml