Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/rv3n
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf rv3n
[Pipeline] sh
+ git clone --recursive https://github.com/risclite/rv3n rv3n
Cloning into 'rv3n'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/rv3n/rv3n
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s rv3n_top -I rtl rtl/define.v rtl/define_para.v rtl/include_func.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v
rtl/include_func.v:19: error: parameter declarations must be contained within a module.
rtl/include_func.v:20: error: parameter declarations must be contained within a module.
rtl/include_func.v:21: error: parameter declarations must be contained within a module.
rtl/include_func.v:22: error: parameter declarations must be contained within a module.
rtl/include_func.v:23: error: parameter declarations must be contained within a module.
rtl/include_func.v:24: error: parameter declarations must be contained within a module.
rtl/include_func.v:26: error: parameter declarations must be contained within a module.
rtl/include_func.v:27: error: parameter declarations must be contained within a module.
rtl/include_func.v:28: error: parameter declarations must be contained within a module.
rtl/include_func.v:29: error: parameter declarations must be contained within a module.
rtl/include_func.v:31: error: parameter declarations must be contained within a module.
rtl/include_func.v:32: error: parameter declarations must be contained within a module.
rtl/include_func.v:33: error: parameter declarations must be contained within a module.
rtl/include_func.v:34: error: parameter declarations must be contained within a module.
rtl/include_func.v:35: error: parameter declarations must be contained within a module.
rtl/include_func.v:36: error: parameter declarations must be contained within a module.
rtl/include_func.v:39: error: function declarations must be contained within a module.
rtl/include_func.v:467: error: function declarations must be contained within a module.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/rv3n/rv3n
[Pipeline] {
[Pipeline] sh
+ rm -rf FPGA LICENSE README.md build diagram.png rtl sim testbench
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 18
Finished: FAILURE