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Start of Pipeline - (10 min in block)
node - (10 min in block)
node block - (5 min 12 sec in block)
stage - (3.2 sec in block)Git Clone
stage block (Git Clone) - (2.7 sec in block)
sh - (0.67 sec in self)rm -rf rv3n
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/risclite/rv3n rv3n
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.86 sec in block)rv3n
dir block - (0.59 sec in block)
sh - (0.4 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2012 -s rv3n_top -I rtl rtl/define.v rtl/define_para.v rtl/include_func.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.85 sec in block)rv3n
dir block - (0.6 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /eda/processor_ci_utils/labels.json
stage - (5 min 4 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 4 sec in block)
parallel - (5 min 3 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (4 min 14 sec in block)colorlight_i9
stage block (colorlight_i9) - (4 min 13 sec in block)
lock - (4 min 13 sec in block)colorlight_i9
lock block - (4 min 12 sec in block)
stage - (3 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 53 sec in block)
dir - (3 min 52 sec in block)rv3n
dir block - (3 min 52 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (3 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p rv3n -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)rv3n
dir block - (15 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p rv3n -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.3 sec in block)
echo - (0.2 sec in self)Testing FPGA colorlight_i9.
dir - (0.86 sec in block)rv3n
dir block - (0.6 sec in block)
sh - (0.41 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_arty_a7_100t) - (5 min 3 sec in block)
stage - (5 min 2 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 2 sec in block)
lock - (5 min 1 sec in block)digilent_arty_a7_100t
lock block - (5 min 0 sec in block)
stage - (4 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 53 sec in block)
dir - (4 min 52 sec in block)rv3n
dir block - (4 min 52 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (4 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p rv3n -b digilent_arty_a7_100t
stage - (5.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)rv3n
dir block - (3.9 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p rv3n -b digilent_arty_a7_100t -l
stage - (1.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.3 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (0.84 sec in block)rv3n
dir block - (0.6 sec in block)
sh - (0.39 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.29 sec in self)**/test-reports/*.xml