Console Output

+ iverilog -o simulation.out -g2005 -s rv3n_top rtl/define.v rtl/define_para.v rtl/include_func.v rtl/mul.v rtl/rv3n_chain_manager.v rtl/rv3n_csr.v rtl/rv3n_func_jcond.v rtl/rv3n_func_lsu.v rtl/rv3n_func_muldiv.v rtl/rv3n_func_op.v rtl/rv3n_gsr.v rtl/rv3n_predictor.v rtl/rv3n_stage_ch.v rtl/rv3n_stage_dc.v rtl/rv3n_stage_id.v rtl/rv3n_stage_if.v rtl/rv3n_top.v
rtl/define.v:50: Include file define_para.v not found
error: Unable to find the root module "rv3n_top" in the Verilog source.
     : Perhaps ``-s rv3n_top'' is incorrect?
1 error(s) during elaboration.