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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rsd -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/rsd/rsd/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Cache/CacheFlushManager.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Cache/DCache.sv:24]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Cache/ICache.sv:10]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Cache/MemoryAccessController.sv:12]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/FloatingPointUnit/FPDivSqrtUnit.sv:4]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/FloatingPointUnit/FPDivSqrtUnitIF.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/IO/IO_Unit.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/LoadStoreUnit/LoadQueue.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/LoadStoreUnit/LoadStoreUnit.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/LoadStoreUnit/StoreCommitter.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/LoadStoreUnit/StoreQueue.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Axi4LiteControlRegister.sv:8]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Axi4LiteControlRegisterIF.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Axi4Memory.sv:8]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Axi4Memory.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Axi4MemoryIF.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/ControlQueue.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/Memory.sv:9]
ERROR: [Synth 8-9263] cannot open include file 'BasicMacros.sv' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/MemoryLatencySimulator.sv:5]
ERROR: [Synth 8-9263] cannot open include file 'SysDeps/XilinxMacros.vh' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/MemoryTypes.sv:4]
ERROR: [Synth 8-10157] use of undefined macro 'MEMORY_AXI4_READ_ID_WIDTH' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/MemoryTypes.sv:60]
ERROR: [Synth 8-10157] use of undefined macro 'MEMORY_AXI4_ADDR_BIT_SIZE' [/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Memory/MemoryTypes.sv:61]
ERROR: [Synth 8-7136] In the module 'Controller' declared at '/var/jenkins_home/workspace/rsd/rsd/Processor/Src/Controller.sv:9', parameter 'CLK_FREQ' used as named parameter override, does not exist [/eda/processor_ci/rtl/rsd.sv:58]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/rsd.sv:5]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 296, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.