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Start of Pipeline - (34 min in block)
node - (34 min in block)
node block - (26 sec in block)
stage - (11 sec in block)Git Clone
stage block (Git Clone) - (11 sec in block)
sh - (0.78 sec in self)rm -rf rocket-chip
sh - (10 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/rocket-chip rocket-chip
stage - (2.3 sec in block)Simulation
stage block (Simulation) - (1.8 sec in block)
dir - (1.3 sec in block)rocket-chip
dir block - (0.94 sec in block)
sh - (0.71 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s src/main/resources/vsrc/AsyncResetReg.v src/main/resources/vsrc/ClockDivider2.v src/main/resources/vsrc/ClockDivider3.v src/main/resources/vsrc/EICG_wrapper.v src/main/resources/vsrc/RoccBlackBox.v src/main/resources/vsrc/SimDTM.v src/main/resources/vsrc/SimJTAG.v src/main/resources/vsrc/debug_rob.v src/main/resources/vsrc/plusarg_reader.v dependencies/chisel/src/test/resources/chisel3/AnalogBlackBox.v dependencies/chisel/src/test/resources/chisel3/BlackBoxTest.v dependencies/chisel/src/test/resources/chisel3/VerilogVendingMachine.v dependencies/hardfloat/hardfloat/tests/resources/vsrc/emulator.v src/main/resources/vsrc/TestDriver.v dependencies/chisel/svsim/src/test/resources/GCD.sv
stage - (0.94 sec in block)Utilities
stage block (Utilities) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (10 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9.5 sec in block)
getContext - (0.27 sec in self)
parallel - (8.9 sec in block)
parallel block (Branch: colorlight_i9) - (59 ms in block)
stage - (7.5 sec in block)colorlight_i9
stage block (colorlight_i9) - (7 sec in block)
getContext - (0.65 sec in self)
stage - (2.5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.6 sec in block)
getContext - (0.15 sec in self)
stage - (1.7 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.59 sec in block)
getContext - (0.17 sec in self)
stage - (1.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.63 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (8.3 sec in block)
stage - (7.4 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (6.9 sec in block)
getContext - (0.62 sec in self)
stage - (2.5 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.72 sec in block)
getContext - (0.17 sec in self)
stage - (1.7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.71 sec in block)
getContext - (0.16 sec in self)
stage - (1.2 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.72 sec in block)
getContext - (0.17 sec in self)
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.53 sec in block)
junit - (0.27 sec in self)**/test-reports/*.xml