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Start of Pipeline - (13 sec in block)
node - (12 sec in block)
node block - (12 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.46 sec in self)rm -rf riskow
sh - (0.92 sec in self)git clone --recursive --depth=1 https://github.com/racerxdl/riskow riskow
stage - (2.1 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
dir - (0.97 sec in block)riskow
dir block - (0.67 sec in block)
sh - (0.46 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v
stage - (0.94 sec in block)Utilities
stage block (Utilities) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (5.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 sec in block)
getContext - (0.27 sec in self)
parallel - (4.4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 sec in block)
stage - (3.6 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.3 sec in block)
getContext - (0.38 sec in self)
stage - (0.94 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.37 sec in block)
getContext - (0.15 sec in self)
stage - (0.91 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.15 sec in self)
stage - (0.69 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.27 sec in self)**/*.xml