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Start of Pipeline - (9 min 39 sec in block)
node - (9 min 39 sec in block)
node block - (9 min 38 sec in block)
stage - (2.1 sec in block)Git Clone
stage block (Git Clone) - (1.7 sec in block)
sh - (0.46 sec in self)rm -rf riskow
sh - (0.91 sec in self)git clone --recursive https://github.com/racerxdl/riskow riskow
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.84 sec in block)riskow
dir block - (0.6 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v
stage - (9 min 32 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9 min 32 sec in block)
parallel - (9 min 31 sec in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (5 min 26 sec in block)colorlight_i9
stage block (colorlight_i9) - (5 min 26 sec in block)
lock - (5 min 25 sec in block)colorlight_i9
lock block - (5 min 24 sec in block)
stage - (4 min 58 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (4 min 55 sec in block)
dir - (4 min 53 sec in block)riskow
dir block - (4 min 52 sec in block)
echo - (0.19 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (4 min 51 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9
stage - (19 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (18 sec in block)
dir - (16 sec in block)riskow
dir block - (16 sec in block)
echo - (0.33 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9 -l
stage - (6.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 sec in block)
echo - (0.22 sec in self)Testando FPGA colorlight_i9.
dir - (5.4 sec in block)riskow
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (9 min 31 sec in block)
stage - (9 min 30 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (9 min 29 sec in block)
lock - (9 min 28 sec in block)digilent_nexys4_ddr
lock block - (9 min 27 sec in block)
stage - (9 min 9 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (9 min 8 sec in block)
dir - (9 min 7 sec in block)riskow
dir block - (9 min 7 sec in block)
echo - (0.16 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (9 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr
stage - (15 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (14 sec in block)
dir - (13 sec in block)riskow
dir block - (13 sec in block)
echo - (0.33 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr -l
stage - (2.2 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1.8 sec in block)
echo - (0.46 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.75 sec in block)riskow
dir block - (0.29 sec in block)
stage - (1.2 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.68 sec in self)**/test-reports/*.xml