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Start of Pipeline - (2 days 23 hr in block)
node - (6 mo 26 days in block)
node block - (6 mo 26 days in block)
stage - (2 sec in block)Git Clone
stage block (Git Clone) - (1.5 sec in block)
sh - (0.46 sec in self)rm -rf riskow
sh - (0.91 sec in self)git clone --recursive https://github.com/racerxdl/riskow riskow
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.84 sec in block)riskow
dir block - (0.6 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v
stage - (6 mo 26 days in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 mo 26 days in block)
parallel - (6 mo 26 days in block)
parallel block (Branch: colorlight_i9) - (56 ms in block)
stage - (6 mo 26 days in block)colorlight_i9
stage block (colorlight_i9) - (6 mo 26 days in block)
lock - (6 mo 26 days in block)colorlight_i9
lock block - (6 mo 26 days in block)
stage - (5 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (5 min 8 sec in block)
dir - (5 min 7 sec in block)riskow
dir block - (5 min 7 sec in block)
echo - (0.15 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (5 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riskow
dir block - (15 sec in block)
echo - (0.16 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9 -l
stage - (6 mo 26 days in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 mo 26 days in block)
echo - (0.25 sec in self)Testando FPGA colorlight_i9.
dir - (6 mo 26 days in block)riskow
dir block - (6 mo 26 days in block)
sh - (2 days 23 hr in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (9 min 6 sec in block)
stage - (9 min 5 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (9 min 5 sec in block)
lock - (9 min 4 sec in block)digilent_nexys4_ddr
lock block - (9 min 3 sec in block)
stage - (8 min 53 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (8 min 53 sec in block)
dir - (8 min 52 sec in block)riskow
dir block - (8 min 52 sec in block)
echo - (0.19 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (8 min 51 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr
stage - (7.1 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.6 sec in block)
dir - (6.2 sec in block)riskow
dir block - (6 sec in block)
echo - (0.18 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr -l
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1 sec in block)
echo - (0.26 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.45 sec in block)riskow
dir block - (0.19 sec in block)