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Start of Pipeline - (10 min in block)
node - (10 min in block)
node block - (10 min in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.2 sec in block)
sh - (0.61 sec in self)rm -rf riskow
sh - (1.2 sec in self)git clone --recursive https://github.com/racerxdl/riskow riskow
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.96 sec in block)riskow
dir block - (0.65 sec in block)
sh - (0.41 sec in self)iverilog -o simulation.out -g2005 -s CPU cpu/alu.v cpu/comp.v cpu/cpu.v cpu/instruction_decoder.v cpu/program_counter.v cpu/register_bank.v
stage - (9 min 55 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9 min 54 sec in block)
parallel - (9 min 54 sec in block)
parallel block (Branch: colorlight_i9) - (57 ms in block)
stage - (53 sec in block)colorlight_i9
stage block (colorlight_i9) - (53 sec in block)
lock - (52 sec in block)colorlight_i9
lock block - (51 sec in block)
stage - (48 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (48 sec in block)
dir - (47 sec in block)riskow
dir block - (47 sec in block)
echo - (0.19 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (47 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b colorlight_i9
stage - (1.1 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.42 sec in block)
getContext - (0.16 sec in self)
stage - (0.8 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (0.42 sec in block)
getContext - (0.17 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (9 min 53 sec in block)
stage - (9 min 52 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (9 min 51 sec in block)
lock - (9 min 50 sec in block)digilent_nexys4_ddr
lock block - (8 min 48 sec in block)
stage - (8 min 39 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (8 min 38 sec in block)
dir - (8 min 38 sec in block)riskow
dir block - (8 min 37 sec in block)
echo - (0.37 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (8 min 36 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr
stage - (7.2 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.7 sec in block)
dir - (6.3 sec in block)riskow
dir block - (6 sec in block)
echo - (0.2 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p riskow -b digilent_nexys4_ddr -l
stage - (1.3 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (1 sec in block)
echo - (0.22 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.5 sec in block)riskow
dir block - (0.18 sec in block)
stage - (1.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1.4 sec in block)
dir - (0.92 sec in block)riskow
dir block - (0.68 sec in block)
sh - (0.42 sec in self)rm -rf *