Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s AtomRV -I rtl/core/ rtl/core/Alu.v rtl/core/AtomRV.v rtl/core/AtomRV_wb.v rtl/core/CSR_Unit.v rtl/core/Decode.v rtl/core/RVC_Aligner.v rtl/core/RVC_Decoder.v rtl/core/RegisterFile.v
rtl/core/AtomRV.v:15: Include file Utils.vh not found
Preprocessor failed with 1 errors.