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Start of Pipeline - (31 sec in block)
node - (30 sec in block)
node block - (29 sec in block)
stage - (3.3 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.9 sec in self)rm -rf riscv-atom
sh - (1.3 sec in self)git clone --recursive --depth=1 https://github.com/saursin/riscv-atom riscv-atom
stage - (3.6 sec in block)Simulation
stage block (Simulation) - (2.5 sec in block)
dir - (1.6 sec in block)riscv-atom
dir block - (1 sec in block)
sh - (0.63 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rtl/core/Alu.v rtl/core/AtomRV.v rtl/core/AtomRV_wb.v rtl/core/CSR_Unit.v rtl/core/Decode.v rtl/core/RVC_Aligner.v rtl/core/RVC_Decoder.v rtl/core/RegisterFile.v rtl/soc/atombones/AtomBones.v rtl/soc/hydrogensoc/HydrogenSoC.v rtl/uncore/gpio/GPIO.v rtl/uncore/gpio/GPIO_old.v rtl/uncore/gpio/IOBuf.v rtl/uncore/mem/DualPortRAM_wb.v rtl/uncore/mem/SinglePortRAM_wb.v rtl/uncore/mem/SinglePortROM_wb.v rtl/uncore/spi/SPI_core.v rtl/uncore/spi/SPI_wb.v rtl/uncore/timer/Timer_wb.v rtl/uncore/uart/FIFO_sync.v rtl/uncore/uart/UART.v rtl/uncore/uart/UART_core.v rtl/uncore/uart/simpleuart.v rtl/uncore/uart/simpleuart_wb.v rtl/uncore/wishbone/Arbiter.v rtl/uncore/wishbone/Arbiter2_wb.v rtl/uncore/wishbone/Arbiter3_wb.v rtl/uncore/wishbone/Crossbar5_wb.v rtl/uncore/wishbone/Crossbar6_wb.v rtl/uncore/wishbone/Crossbar_wb.v rtl/uncore/wishbone/Priority_encoder.v rtl/tb/HydrogenSoC_tb.v
stage - (1.9 sec in block)Utilities
stage block (Utilities) - (0.74 sec in block)
getContext - (0.32 sec in self)
stage - (18 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (16 sec in block)
getContext - (0.55 sec in self)
parallel - (15 sec in block)
parallel block (Branch: colorlight_i9) - (0.1 sec in block)
stage - (12 sec in block)colorlight_i9
stage block (colorlight_i9) - (12 sec in block)
getContext - (1.4 sec in self)
stage - (3.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.1 sec in block)
getContext - (0.32 sec in self)
stage - (3.3 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (1.1 sec in block)
getContext - (0.31 sec in self)
stage - (2.3 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.1 sec in block)
getContext - (0.32 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (14 sec in block)
stage - (12 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (11 sec in block)
getContext - (1.3 sec in self)
stage - (3.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.4 sec in block)
getContext - (0.33 sec in self)
stage - (3.3 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (1.3 sec in block)
getContext - (0.31 sec in self)
stage - (2.3 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (1.3 sec in block)
getContext - (0.34 sec in self)
stage - (1.5 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml