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Start of Pipeline - (2 min 31 sec in block)
node - (2 min 30 sec in block)
node block - (2 min 30 sec in block)
stage - (2.5 sec in block)Git Clone
stage block (Git Clone) - (2 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf riscado-v
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.84 sec in block)riscado-v
dir block - (0.59 sec in block)
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)riscado-v
dir block - (0.6 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (2 min 23 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (2 min 22 sec in block)
parallel - (2 min 22 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (2 min 22 sec in block)
stage - (2 min 21 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (2 min 21 sec in block)
lock - (2 min 21 sec in block)digilent_arty_a7_100t
lock block - (2 min 20 sec in block)
stage - (2 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2 min 7 sec in block)
dir - (2 min 7 sec in block)riscado-v
dir block - (2 min 7 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (2 min 6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p riscado-v -b digilent_arty_a7_100t
stage - (5.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.7 sec in block)
dir - (4.3 sec in block)riscado-v
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p riscado-v -b digilent_arty_a7_100t -l
stage - (6.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (6.4 sec in block)
echo - (0.15 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.45 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.6 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.27 sec in self)**/*.xml