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Start of Pipeline - (19 min in block)
node - (19 min in block)
node block - (13 min in block)
stage - (3 sec in block)Git Clone
stage block (Git Clone) - (2.5 sec in block)
sh - (0.79 sec in self)rm -rf riscado-v
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.86 sec in block)riscado-v
dir block - (0.61 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
stage - (1.8 sec in block)Utilities
stage block (Utilities) - (1.3 sec in block)
dir - (0.91 sec in block)riscado-v
dir block - (0.66 sec in block)
sh - (0.43 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels
stage - (13 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (13 min in block)
parallel - (13 min in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (6 min 59 sec in block)colorlight_i9
stage block (colorlight_i9) - (6 min 59 sec in block)
lock - (6 min 58 sec in block)colorlight_i9
lock block - (6 min 57 sec in block)
stage - (6 min 38 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (6 min 37 sec in block)
dir - (6 min 37 sec in block)riscado-v
dir block - (6 min 37 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (6 min 36 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)riscado-v
dir block - (15 sec in block)
echo - (0.15 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 -l
stage - (2.1 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.8 sec in block)
echo - (0.21 sec in self)Testing FPGA colorlight_i9.
dir - (1.3 sec in block)riscado-v
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyACM0"
sh - (0.4 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyACM0
parallel block (Branch: digilent_arty_a7_100t) - (13 min in block)
stage - (13 min in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (13 min in block)
lock - (13 min in block)digilent_arty_a7_100t
lock block - (12 min in block)
stage - (12 min in block)Synthesis and PnR
stage block (Synthesis and PnR) - (12 min in block)
dir - (12 min in block)riscado-v
dir block - (12 min in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (12 min in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_arty_a7_100t
stage - (5.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.6 sec in block)
dir - (4.2 sec in block)riscado-v
dir block - (4 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_arty_a7_100t -l
stage - (2.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.8 sec in block)
echo - (0.2 sec in self)Testing FPGA digilent_arty_a7_100t.
dir - (1.3 sec in block)riscado-v
dir block - (1 sec in block)
sh - (0.46 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (0.39 sec in self)python3 /eda/processor_ci_tests/test_runner/run.py --config /eda/processor_ci_tests/test_runner/config.json --port /dev/ttyUSB1
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.29 sec in self)**/test-reports/*.xml